1. Field of the Invention
The present invention generally relates to CMOS (complimentary metal oxide semiconductor) inverter circuits and more particularly to a method and apparatus for calibrating CMOS inverter circuits.
2. Description of Related Art
Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as MOS (metal-oxide semiconductor) transistor, PMOS (p-channel MOS) transistor, NMOS (n-channel MOS) transistor, CMOS, “operational amplifier,” “common-mode,” “differential-mode” “transconductance,” “output resistance” “gate,” “source,” “drain,” “saturation region,” “trip point,” “bulk,” “cascode,” “switch,” “voltage,” “current,” “circuit,” “circuit node,” “power supply,” “ground,” “rail,” “latch,” “negative resistance,” and “inverter”. Terms and basic concepts like these are apparent from prior art documents, e.g. text books such as “Design of Analog CMOS Integrated Circuits” by Behzad Razavi, McGraw-Hill (ISBN 0-07-118839-8), and thus will not be explained in detail here.
CMOS inverters can be used to embody an operational amplifier. As shown in FIG. 1, an inverter-based operational amplifier 100 comprises: CMOS inverter 111 for receiving voltage VA and output voltage VC; CMOS inverter 112 for receiving voltage VB and output voltage VD; and a latch circuit 130 comprising cross-coupling CMOS inverters 131 and 132 for providing a cross-coupling between VA and VB. The latch circuit 130 is introduced to provide a negative resistance between circuit nodes 101 and 102 to compensate for an otherwise resistive load 120 seen between circuit nodes 101 and 102. The principle of inverter-based operational amplifier is well described by Zeller et al in “A 0.039 mm 2 inverter-based 1.82 mW 68.6 dB-SNDR 10 MHz-BW CT-ΣΔ-ADC in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, VOL. 49, NO. 7, July 2014, and thus not described in details here.
For an inverter-based operational amplifier 100 to have high performance, the negative resistance provided by the latch circuit 130 must match well with the otherwise resistive load 120. A calibration is needed to tune the CMOS inverters 131 and 132 within the latch circuit 130 to ensure the negative resistance that the latch circuit 130 provides matches well with the resistive load 120. Although Zeller et at in the aforementioned paper taught a method to calibrate CMOS inverters 131 and 132, the method is based on a “common-mode” calibration scheme, where a common-mode signal is injected into both circuit nodes 101 and 102 (to make VA and VB both change in the same direction by the same amount) and a resultant mean value of VC and VD is observed and used as a basis for tuning CMOS inverters 131 and 132. In actual applications, however, what is of interest is a “differential-mode” signal, where VA and VB change in opposite directions.
A CMOS inverter comprises a NMOS transistor and a PMOS transistor. When operating in the “saturation region” as an amplifier, a MOS transistor, either PMOS or NMOS, behaves as a transconductance device with a finite output resistance; the output resistance is often neglected and assumed infinite for ease of analysis but needs to be considered if one seeks to perform an accurate calibration. In a common-mode input scenario, VA and VB both change in the same direction with the same amount; in this case, both the transconductance and the output resistance of every MOS device within CMOS inverters 131 and 132 react to resist that change. In a differential-mode input scenario, VA and VB change in opposite directions; in this case, the transconductance (of every MOS device within CMOS inverters 131 and 132) reacts to assist the change while the output resistance (of every MOS device within CMOS inverters 131 and 132) still reacts to resist the change. In other words, the output resistance effectively enhances the transconductance in the common-mode input scenario, but effectively weakens the transconductance in the differential-mode input scenario. The calibration scheme taught by Zeller et al, neglects the effect of the output resistance, and thus is not accurate for the differential-mode operation of interest.